Metal-oxide semiconductor (MOS) transistors are used in many integrated circuit designs, serving as switches to open and close the circuits. In general, a MOS transistor comprises a source region and a drain region connected by a channel, and a gate region separated from the channel by a gate dielectric. The channel can comprise an n-type or p-type semiconductor material, forming an n-channel MOS (NMOS) or a p-channel MOS (PMOS) transistor, respectively.
In U.S. Pat. No. 6,573,169 issued to Noble et al., entitled “Highly Conductive Composite Polysilicon Gate for CMOS Integrated Circuits,” (hereinafter “Noble”), a method is disclosed for making a low-resistance gate structure for NMOS or PMOS transistors. Namely, in Noble, a polysilicon gate is formed over a gate insulation layer. A metal-substitution reaction is used to diffuse a metal into the gate. The same general process, with variations in doping, is used to form the gates for either the NMOS or PMOS transistors.
In many applications, a combination of NMOS and PMOS transistors are integrated into a common device. By way of example only, logic gate devices typically include linked NMOS/PMOS transistor pairs that act as switches between logic states. In U.S. Pat. No. 7,045,456 issued to Murto et al., entitled “MOS Transistor Gates with Thin Lower Metal Silicide and Methods for Making the Same” (hereinafter “Murto”), NMOS and PMOS transistors are used in a common complementary-metal-oxide semiconductor (CMOS) device, wherein a gate is formed for each of the NMOS and PMOS transistors by a series of reaction steps to form a fully silicided gate electrode over a gate dielectric. As with Noble, in Murto, the NMOS transistor and PMOS transistor gates are formed by the same general process, with variations in doping.
In some applications, however, it is desirable to employ NMOS transistors and PMOS transistors in a common device that have different gate structures from one another. Varying the gate structure can help to optimize the work function of each transistor type. For example, a certain gate structure can be used to optimize the work function of the NMOS transistors, while a different gate structure can be used to optimize the work function of the PMOS transistors.
Thus, techniques for integrating NMOS and PMOS transistors having different gate structures within a common device would be desirable.